In FIG. 1, the prior art, shared pixel schematic comprises two photodetectors (PD1 and PD2), two transfer gates (TG1 and TG2), a row select transistor (RSEL), a common floating diffusion sense node (FD), a reset transistor with a reset gate (RG) and a source follower input transistor (SF). The prior art pixel of FIG. 2 is a similar concept except that four PDs and TGs share common components.
These designs created coupling capacitance between the TGs and FD that produced a fixed pattern noise that is correlated to the mismatch in the capacitance of each of the TGs to the common FD. For example, if the capacitance in from TG1 to FD (CTG1-FD) in the pixel in FIG. 1 was different than that of TG2 to FD (CTG2-FD), then there would be a row correlated odd-even, or modulo-2, fixed pattern noise during readout associated with the mismatch of the aforementioned capacitances.
A similar effect is noted in the 4-shared pixels as shown in FIG. 2. The mismatch in the capacitances (CTG1-FD), (CTG2-FD), (CTG3-FD) and (CTG4-FD) led to a row correlated modulo-4 fixed pattern noise. Because the fixed pattern noise is highly spatially correlated it is very easy to detect at low levels and degrades image quality. The TG-FD capacitances include the TG overlap capacitance and the parasitic capacitances associated with the interconnect within the pixel.
The present invention eliminates the fixed pattern noise by doing detailed layout and design to produced matched capacitances for TGi to FD for shared amplifier pixels. This can be done by, but not limited to, identical placement of TG wiring and use of the same level of interconnect within each pixel with respect to the FD junction areas and interconnect. Use of post layout extraction tools and other integrated circuit capacitance modeling tools can be used to design the required level of matching. In some cases this could require purposeful addition of parasitic capacitance to one or more TGi-FD regions to produce matched TG-FD coupling capacitance.